1. Field of the Invention
The invention relates to a method of forming a via, and more particularly, to a method of forming an unlanded via penetrating through an inter-metal dielectric (IMD).
2. Description of the Related Art
As the integration of semiconductor devices increase, the dimensions of devices cannot supply enough area for interconnection. To match the requirements of the metal oxide semiconductor (MOS) devices with smaller dimensions, designs of multilevel interconnections are adapted in most of the integrated circuits (ICs). Normally, an inter-metal dielectric (IMD) layer is used to isolate two conductive layers. By the formation of a via, the conductive layers are electrically connected.
In FIG. 1A to FIG. 1E, a conventional method of forming a via penetrating an inter-metal dielectric layer is shown. In FIG. 1A, a substrate 10 having a conductive layer 11, for example, a metal layer or a poly-silicon layer, formed and defined thereon is provided. In FIG. 1B, an inter-metal dielectric layer 12 is formed over the substrate 10 by chemical vapor deposition (CVD), for example, by atmosphere pressure CVD (APCVD), low pressure CVD (LPCVD), or plasma-enhanced CVD (PECVD).
In FIG. 1C, to achieve a global planarization, the inter-metal dielectric layer 12 is polished by chemical-mechanical polishing (CMP).
In FIG. 1D and FIG. 1E, forming a photo-resist layer 13 on the inter-metal dielectric layer 12. Using photolithography and etching, the photo-resist layer 13 is defined to form an opening 14, so that the conductive layer 11 is exposed therewithin. The etching is divided into two stages. In the first stage, a main etching is performed. The etching time is estimated in accordance with the material of the inter-metal dielectric layer 12. In the second stage, an over etching is performed. In the first stage, a residue of the inter-metal dielectric layer 12 is remained within the opening 14, so that a poor contact to the conductive layer 11 is caused. Therefore, the second stage is performed to ensure a proper contact to the conductive layer 11. The etching time in the second stage is normally shorter than that in the first stage.
In FIG. 1F, the photo-resist layer 13 is removed. A conductive layer is formed on the inter-metal dielectric layer 12 and fills the opening 14. Using dry etching or chemical-mechanical polishing, the conductive layer is etched back to form a via 16. A metal layer 15 is then formed on the inter-metal dielectric layer 12. The electrical connection between the conductive layer 11 and the metal layer 15 is performed by the conductive layer 16 within the opening 14.
Since the etching time is estimated in accordance with the material of the inter-metal dielectric layer, in case of a multi-layer structure or improper time control, a proper contact cannot be obtained. In particularly, as semiconductor devices are designed and developed towards a smaller and smaller dimension, the opening for forming a via becomes narrower and narrower. The aspect ratio is thus larger. In case that etching time is too short, a poor contact occurs as shown in FIG. 2. On the other hand, if a misalignment occurs between the opening and the conductive layer or the etching time is controlled to long, a short circuit occurs as shown in FIG. 3. Moreover, if moisture is absorbed, a void is form in the via.